The invention relates to comparators, and more particularly, to comparators outputting offset calibration.
In various analog/digital converters (ADC) such as flash ADC, interpolation ADC, pipeline ADC and two-step ADC and high speed receivers such as PCI express receivers and DVI receivers, high speed comparators are often required to fulfill the requirements of high speed operation of the digital circuit.
Differential logic circuits, such as MOS current mode logic (MCML) circuits, are suitable for high speed systems because of high switching speed and low power consumption. FIGS. 1a and 1b are circuit diagrams of conventional MCML circuits. If the threshold voltage (Vth) of the transistor MN1 differs from that of the transistor MN2, output signal of the MCML circuit becomes unbalanced by bias offset voltages. Namely, the MCML circuit includes output offsets at the output terminal thereof. The MCML circuit may operate improperly if the minimum differential output voltage is too low. Thus, the maximum operating frequency and resolution power of the MCML circuit are limited by manufacturing fluctuations, such as fluctuations of the threshold voltage (Vth) of the differential pair transistors. Further, the output common mode level of MCML circuit is inconsistent.